X-ISCKER - IPCore

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Introduction
Basics
RISCKER
RISCKER Source
RISCKER Observer
RISCKER  Applications
CISCKER
CISCKER Source
CISCKER Observer
CISCKER Applications
X-ISCKER IDE
Documentation
Tutorial
Future
Authors

XISCKER: Reduced and Complex Instruction Set Computing Key Educational Resources
A Configurable Platform for the Emulation of Different Computer Architectures
An introduction to Computer Architectures through digital design description for FPGA devices
 
Computer Architecture embraces all three aspects of a processor design: instruction set, functional estructure and hardware implementation. The main architectures are RISC (Reduced Instruction Set Computing) and CISC (Complex Instruction Set Computing) which led to x86 as we still recognize now. Both designs bring electronics or computer science students the basic concepts they should learn.
 
Therefore, this project brings an opportunity to learn this basic concepts through the HDL description in Verilog of two processors (One for each architecture) implemented on FPGA devices, together with strong documentation, common assembly language instructions and support software.
 
The main goal is that any modification to the instructions, performance optimization, compression, etc. is shared and described so we can all learn from it.
 
The reason behind this project...
 
Some Computer Architecture courses are limited to the explanation of a certain commercial processor, but the information from the manufacturer won't reveal its internal organization details, which should be the main subject to discuss in such course or project. On the other hand, commercial processors have many specific functions (For compatibility with older devices) which may be a pain in the back to understand.
 
An alternative to this kind of resources are simulators, which are very detailed on documentation, but in the end they cannot be implemented.
This makes it difficult to find a device that provides all documentation of its internal design, to be open to modifications and which can also be implemented in an electronics or computing project with other purposes than just academic.
 
In other words, perfectly detailed and applicable.
 
What is a Processor?

The processor or CPU is the active part in a digital computer. Its principal function is to do operations (control, logical, arithmetical or transfer) between data input and memory data or registers.
 
A microprocessor is based on four basic units: CU (Control Unit), ALU (Arithmetic-Logic Unit), MU (Memory Unit) and I/O Unit. Its basic functionality is to Fetch, Decode and Execute instructions from the memory unit, which are represented by an Operation Code (OpCode) and a set of operands.
 
The interconnection between all this units and the rest of the subsystems found in a processor is known as Datapath. Control signals from the CU choose where data is meant to go through the datapath according to the instructions and other state conditions. This instructions can perform assignation operations (Logic and Arithmetic) and program flow control (Jumps and Branches).
 
What is Computer Architecture?
 
Computer Architecture determines the which attributes are important for a processor's performance while keeping cost and power low. This process includes three levels in which to design a processor: The Instruction Set, Functional Organization and Hardware Implementation.
 
    What is ISA?

    
ISA (Instruction Set Architecture) is the highest level of abstraction for the hardware-software description of a processor system. The ISA is the design of
 a composition of standard mnemonics to make it easier for programmers to write and debug a computing program without thinking in machine code level, logic gate level or transistor level.
 
    What is Computer Organization?
 
Is the functional specific performance of every component and the interconnection between them. Two processors can have the same ISA but diferent computer-organization like the AMD opteron and Intel Pentium 4. The program is the same for both, but the programmer doesn't know how it is executed inside each processor.
 
What is Hardware Implementation?
 
Hardware implementation is the lowest level of abstraction and it is in charge of the circuital design. It determines the electronic technology and physical aspects of the microprocessor like, clock frequencies, memory systems and power consumption through a set of requirements specified by the application.
 

CISC

CISC

Complex Instruction Set Computing
 
A CISC architecture processor has a few registers (Accumulator, Program Counter, Index register, Stack Pointer, Condition Code Register) with especific functions, a lot of variable size instructions and addresing modes which result in shorter programs. They require a big unit control and more clock cycles per instruction. Each CISC instruction is subdivided in smaller instructions called micro-instructions, they are put together in a specific order to execute the instruction.

RISC

RISC

Reduced Instruction Set Computing
 
A RISC processor has a few fixed size instructions, a lot of general purpose registers but a few addresing modes. They have a simpler control unit with a smaller circuit area which leads to high speed execution instruction.

 

MSc. Alonso Retamoso's 4bit Architecture
 
 
 

Instruction

[Label] : [Operation] [Rd], [Rs], [Rt], #[Imm/Dir] ;[Comment]

Examples

beq rg1, rg0, #16 ;Branch to address 16 if rg1 and rg0 are equal

lw rg3, r0, #0 ;Load word in rg3 to the address r0+0

inc op ;Increment the Ouput Port Register

 

Feature RISCKER
# of Instructions 30
# of Registers 64
ALU 16 bits
Memory Architecture Harvard
Instructions Size Fixed: 32-bits
Multiplication and Division Dedicated Hardware Units
Shift Operations Barrel Logic, Arithmetic and Rotation
Addressing Modes Immediate,Direct, Indirect,Indexed
Maximum Memory Size 65536x32bits 65536x16bits
# of Branch Conditions 2
Timers 2x16bit
Interruptions 2 by Timer and 2 External
Control Unit HCU
Similar architecture MIPS
# of Registers Name Index Description
1 r0 0 Value 0
8 rv0-rv7 01:08:00 Return Value
8 rp0-rp7 09:16:00 Subroutine Arguments
8 rt0-rt7 17:24:00 Temporary use Registers
22 rg0-rg21 25-46 General Purpose
4 ra0-ra3 47-50 Return Address
1 sp 51 Stack Pointer
2 pr1-pr2 52-53 Timers Period
2 ti1-ti2 54-55 Timer Interruptions Address
2 eir1-eir2 56-57 External Interruptions Address
1 op 58 Output Port
1 rc 59 Control
2 tmr1-tmr2 60-61 Timer values
1 ip 62 Input Port
1 ipc 63 Interruption PC
64      
Modifiable      
Special Purpose      
Read-Only      

 

Control Register

 

[0:1]  TIRST<1,2> = Timer Interrupt Reset Flag
[2:3] EIRST<1,2> = External Interrupt Reset Flag
[4:5] TIE<1,2> = Timer Interrupt Enable
[6:7]   EIE<1,2> = External Interrupt Enable
[8:9] PR1<1,2> = Timer1 Prescaler
[10:11]  PR2<1,2> = Timer2 Prescaler
[12:13]  TMRE<1,2> = Timer Enable
[14:15]  TRST<1,2> = Timer Reset

       

       

       

       

       

   

     

    

 

Instructions Set

Operation Operands Description
R-Type
add Rd, Rs, Rt

Rd, Rt		 Rd = Rs + Rt Rd = Rd + Rt
and Rd = Rs & Rt Rd = Rd & Rt
or Rd = Rs | Rt Rd = Rd | Rs
xor Rd = Rs ^ Rt Rd = Rd ^ Rs
nand Rd = ~(Rs & Rt) Rd = ~(Rd & Rs)
nor Rd = ~(Rs | Rt) Rd = ~(Rd | Rs)
sub Rd = Rs - Rt Rd = Rd - Rs
neg Rd,Rs
Rd		 Rd = -Rs Rd = -Rd
inc Rd = Rs + 1 Rd = Rd+1
mult Rd,Rs,Rt

Rd,Rt		 Rd[15:0] = Rs[7:0] * Rt[7:0]
Rd[15:0] = Rd[7:0] * Rs[7:0]
div Rd = {Rs[15:0] / Rt[15:0],Rs[15:0] % Rt[15:0]}
Rd = {Rd[15:0] / Rs[15:0],Rd[15:0] % Rs[15:0]}
rot Rd, Rt, shamt

Rd,shamt		 Rd = Rt rotates left by shamt Rd = Rd rotates left by shamt
sll Rd = Rt << Shift Amount Rd = Rd << Shift Amount
srl Rd = Rt >> Shift Amount Rd = Rd >> Shift Amount
sra Rd = Rt>>Arithmetic by shamt Rd = Rd>>Arithmetic by shamt
I-Type
addi Rd,Rs,imm

Rd,imm		 Rd = Rs + imm Rd = Rd + imm
andi Rd = Rs & imm Rd = Rd & imm
ori Rd = Rs | imm Rd = Rd | imm
xori Rd = Rs ^ imm Rd = Rd ^ imm
nandi Rd = ~(Rs & imm) Rd = ~(Rd & imm)
nori Rd = ~(Rs | imm) Rd = ~(Rd | imm)
multi Rd = Rs[15:0] * imm Rd = Rd[15:0] * imm
divi Rd,Rs,imm
Rd, imm		 Rd = {Rs[15:0] / imm, Rs[15:0] % imm}
Rd = {Rd[15:0] / imm, Rd[15:0] % imm}
I-Type
sw Rd, Rs, imm
Rd, imm		 Memory[Rs+imm] = Rd
Memory[Rd+imm] = Rd
lw Rd, Rs, imm
Rd, imm		 Rd = Memory[Rs+imm]
Rd = Memory[Rd+imm]
blt Rd, Rs, target ((Rd-Rs)<0) ? PC = target
beq Rd, Rs, target
Rd, target		 ((Rd-Rs)=0) ? PC = target
((Rd-Rd)=0) ? PC = target
J-Type
j target PC = target
jrlw Rs, Rd, imm
Rd, imm		 PC = Rs ; Rd = imm
PC = Rs ; Rt0 = 0
jal Rd, target Rd = PC+1; PC = target

RISCKER Source

A RISC processor instruction set and organization is designed so that it represents this architecture’s characteristics, such as: 
  •     A large amount of registers
  •     Few instructions of the same width
  •     Logical-arithmetic operations only between registers
 
 
 
The processor's structure is similar to the Multi-cycle MIPS described by Patterson and Hennessy in order to facilitate the change between this system and a commercial MIPS-based processor in terms of code compatibility and structural behavior.
 
Along with the individual files there is an Archive containing the latest version of the full system.
 
For a Debugging-Compatible version of this processor go to RISCKER Observer.

RISCKER Observer

This is a Debugging-Compatible hardware version of the RISCKER processor. It includes the necessary modules to create a serial connection through a UART protocol between the processor and the Observer tool in the X-ISCKER IDE software.
 
 
To download the latest version of all Verilog files use the *.zip Archive.
A Project *.qar (Quartus Archive) is provided for implementation in Terasic's DE0-Nano Development Board.
 
You can find the UART module on verilog here: Download UART Module

Applications

This is a space available for code applications created for the RISCKER processor. This includes: Program examples, Libraries, Macros, etc.
 
 

 

 

Instruction

[Label]: [Operation] [Operand],[Addressing Mode] ;[Comment]

 

Examples

 

ADDA #10, IX ;Add ACCA with Memory[IX+10]


INCA ;Increment ACCA 

Feature CISCKER
# of Instructions 244
# of Registers 4
ALU 16bits
Memory Architecture Von Neumann
Instructions Size Variable: 8 to 24-bits
Multiplication and Division Iterative
Shift Operations 1bit Logic, Arithmetic and Rotation
Addressing Modes INH,REL,IMM,DIR,EXT,IX,IX+
Maximum Memory Size 65536x16bits
# of Branch Conditions 14
Timers 2x16 bits
Interruptions 2 by Timer and 2 External
Control Unit MCU
Similar architecture HC08 and HC11 Freescale

                                                                

Control Registers Bits

 

 

 

 

 

 

 

 

   Instructions Map

 

Memory Map

    

CISCKER Source

This CISC processor is based on the instruction set of the Motorola (now Freescale) HC08 and HC11 series which symbolizes the characteristics of CISC architecture, with features like: 
  •     Small set of registers with specific purposes
  •     Several addressing modes
  •     A large amount of instructions with different widths
Along with the individual files there is an Archive containing the latest version of the full system.
 
 
 
For a Debugging-Compatible version of this processor go to CISCKER Observer.

CISCKER Observer

This is a Debugging-Compatible hardware version of the CISCKER processor. It includes the necessary modules to create a serial connection through UART protocol between the Processor and the Observer tool in the X-ISCKER IDE software.
 
To download the latest version of all Verilog files use the *.zip Archive.
A Project *.qar (Quartus Archive) is provided for implementation in Terasic's DE0-Nano Development Board.
 
 
You can find the UART module on verilog here: Download UART Module

This is a space available for code applications created for the CISCKER processor. This includes: Program examples, Libraries, Macros, etc

 Download this file (CISCKER_LIB.zip)CISCKER_LIB.zip

Download this file (test1.ckr)test1.ckr

An IDE (Integrated Development Environment) is a must-have tool for software development. It must be capable of providing the user with assembling, programming and debugging tools in order to develop and test any software project for a given hardware.

 
X-ISCKER IDE v1.0 provides all mentioned functionalities distributed in three tools:
    X-ISCKER ASM (Assembling and Linking with Errors detection)
    X-ISCKER Programmer (Programming Software-Hardware)
    X-ISCKER Observer (Debugging through empirical observation) 
        Note: The Observer tool requires the RISCKER Observer and CISCKER Observer Verilog descriptions with a UART communication module.
 
This IDE was developed using Visual Basic on Visual Studio 2010, which enabled the use of high-level string-processing functions in order to perform the lexical analysis of the Assembly Language instructions for each processor (RISCKER and CISCKER).
 
Changelog:
 
X-ISCKER IDE v1.1: First publication of the IDE with bugs fixed.
 
 
 
 
 
 
 

Documentation

Apart from the overview given in this website, this section provides the Datasheets and User Manuals necessary for the implementation of the XISCKER Platform.
 
Note: Documentation is only available in Spanish to this date. We are working on the translation.
 
Platform FPGA Resources Used Available* Percentage
CISCKER Total LEs 1,436





22,320		 6%
Combinational Functions 1,388 6%
Registers 362 2%
RISCKER Total LEs 2,750 12%
Combinational Functions 2,428 11%
Registers 1,089 5%
CISCKER
Observer		 Total LEs 2,173 10%
Combinational Functions 2,062 9%
Registers 832 4%
RISCKER
Observer		 Total LEs 3,436 15%
Combinational Functions 3,140 14%
Registers 1,643 7%

 

Download this file (ANEXO_A_GuiaDeUsuario.pdf) ANEXO_A_GuiaDeUsuario.pdf      
Download this file (ANEXO_B_HojaDeDatosRISCKER.pdf) ANEXO_B_HojaDeDatosRISCKER.pdf      
Download this file (ANEXO_C_HojaDeDatosCISCKER.pdf) ANEXO_C_HojaDeDatosCISCKER.pdf
Download this file (Thesis Book.pdf)Thesis Book.pdf

https://biblioteca.bucaramanga.upb.edu.co/application/index/material/24051
 

Observer Tutorial (Altera)
  1. Acquiring the processor HW
    1. Download the Quartus Archive (*.qar) according to the processor you want to use.
    2. Extract the *.qar contents in a folder with a Quartus-compatible path (no spaces or special characters)
    3. Open the Quartus Project (*.qpf)
    4. Compile the design and program your FPGA.
  2. Acquiring the SW
    1. X-ISCKER IDE's latest version is in the X-ISCKER IDE tab of this website.
    2. Download the latest version of the Installer *.zip
    3. Extract the *.zip
    4. Install on any Windows PC by double-clicking the "setup" file
      • Requires .NET and a serial COM connection (VCOM USB is recommended through a Serial-USB converter)
  3. Execute the X-ISCKER IDE
    1. If it is the first time, select a workspace folder.
    2. Select the architecture.
    3. Write the assembly code on the left text box (use the proper syntax for each architecture).
    4. Save the Assembly File for future use.
    5. Click on “Run” (F5), To generate the memory file.
    6. You can check the summary tap for more information on the assembly process.
    7. Save the memory file on the Quartus project folder.
    8. Click on “Programmer” (F7).
      1. Select the bin path.
      2. Select the family device.
      3. Select the driver cable for Altera.
      4. Select the path of the project with the processor.
      5. On Altera: select the*.qpf file
      6. On Xilinx: select the top module (Verilog o VHDL).
      7. Click on “Program”

RTOS
 
C Compiler
 
Multi-platform Assembler (Java)
 
DISC
 
VLIW
 
Multi-core
 
Real Time Configuration
 
New Architectures

Prof. Alonso de Jesus Retamoso Llamas

Alfredo Gualdrón: agualdro [at] gmail.com 

Jose Pablo Pinilla: jpablo.pinilla [at] gmail.com