Pynq-z2: Hello world
In this tutorial we will implement a simple test of the inputs/outputs available on our board, in order to familiarize with it and test that we can program it without any issues.
Module and inputs/outputs declaration
Port names on our top module must match names in our io.xdc
Internal wires for connecting test modules to some of our IOs
Clocking wizard. Will take an onboard clk of 125MHz (sysclk), and generate our design clk. This is a xilinx IP core, so we will have to create an instance of it first.
Virtuail IO. Will allow us to capture and generate signals from vivado. This is a xilinx IP core, so we will have to create an instance of it as well
Assignment of onboard buttons, switches to VIO inputs
Assignment of VIO outputs to onboard LEDs
PACKAGE_PIN <pin>specifies a pin on the FPGA
IOSTANDARD <iostandard> specifies the voltage level of the pin
specifies a port from the top level (top.v) to connect to
Basically each line maps a port to a FPGA pin, and specifies its IO type.
Note that port arrays need to be mapped one by one
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