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In this manual you will learn to create a shared library(.so) for your embedded Intel ARM SoC using ARM Development Studio IDE . so you can use on Python on your Linux on you Intel ARM SoC.

Motor PWM module, verilog

motor encoder verilog

This DAC(MCP4821) module was developed by the UPB students Jose Velandia & Henry Lizaro in the year 2012, you can see here the description of the module, plus a very useful application on digital modulations(ASK, FSK, BPSK, QPSK), that you could use to learn more about digital modulations and to visualize at the output of the MCP4821 DAC.

Computer Architecture embraces all three aspects of a processor design: instruction set, functional estructure and hardware implementation. The main architectures are RISC (Reduced Instruction Set Computing) and CISC (Complex Instruction Set Computing) which led to x86 as we still recognize now. Both designs bring electronics or computer science students the basic concepts they should learn. Therefore, this project brings an opportunity to learn this basic concepts through the HDL description in Verilog of two processors (One for each architecture) implemented on FPGA devices, together with strong documentation, common assembly language instructions and support software.

In this manual you are going to understand how the N64 Controller works, and how we can acquire through a simple Finite State Machine (FSM), all the buttons states from the N64 controller using the DE0-NANO (you can use any FPGA board, and implement this manual).

IMPLEMENTATION OF A PID CONTROLLER EMBEDDED IN A FPGA FOR POSITIONING A DC MOTOR

Matrix Multiplication and Gaussian Elimination C optimization.

HLS, OpenCL, MyHDL, Heuristics, FPGA, Nios II, Holguer.

Compile Petalinux for ZCU106 10G Ethernet Example

Emulate the strokes of the keyboard to shutdown your friend's computer. Using Seeeduino Xiao.

This manual is composed by two sections: Hardware description part. In this part you can learn how to create a video acquisition system using Qsys. Software part. In this part you will learn how to communicate with the D5M camera using Nios II through the "Audio and Video config" core. D5M Camera, Cyclone V GX, Holguer, 1080p, Verilog

FreeRTOS,Accelerometer, python, C, Nios II, UART

VGA Retro Sprites, Sound Synthesis, DE0-NANO, FPGA, Retro

Based on Gregory Estrade's Work. I have ported the PC Engine System on the DE0-NANO back in 2014, why don't you have a look?, Maybe port it on another FPGA? Here you go the DE0-NANO (Download:Sources) Ready to be Synthesized.

Nios II Custom Hardware - DE0-NANO-SOC

Introduction - DE0-NANO-SOC

In this manual you are going to understand how the SNES Controller Works, and how we can acquire through a simple Finite State Machine (FSM), all the buttons states from the SNES controller using the de0-nano SOC (you can use any FPGA borad, and implement this manual).

FPGA, Nios II, DE0-NANO-SOC

Pipeline - DE0-NANO-SOC

Nios II, UCOSII, OS, FPGA, DE0-NANO

Bresenham's Algorithm, DE0-NANO-SOC, FPGA, VERILOG

FPGA, Nios II Hardware, Qsys, Quartus, DE0-NANO-SOC, QAR

Non-volitle, Nios II, FPGA, DE0-NANO-SOC

Simulation and FSM Design - DE0-NANO-SOC

VGA, DE0-NANO-SOC, FPGA, Verilog