FPGA lover - FPGA lover

: Category: OS; Published: 13 July 2017; Hits: 216400

Linux

Written by Holguer Andres

Requirements:

DE0-NANO-SOC with and SD-CARD preloaded with the following Linux Image (compiled and customized by Holguer Andres).
Putty.

Procedure:

Using putty open the Linux Terminal through the UART port at 115200 bps.
On the Console type:
```
nano /etc/inittab
```
As you can observe in the next image, and highlighted in red, all the initial system processes init with ":sysinit:" and next to this a command or a script that is going to be run on the initialization of the system.
To see how it works, we are going to modify the file rcS by typing the following:
```
nano /etc/init.d/rcS
```
once you have typed the previous console line, the nano editor is going to show you on the console the file rcS, and you are going to add the line highlighted in red 'fpgalover.com'
Now save and exit.
Type on the console 'reboot' to restart the system
```
reboot
```
once the system is relaunched, you will see at the beginning a new line message that contains what you just have written on the rcS file.
Now it is your time to add your own script to the inittab file and execute what you desire!

References

Welcome to FPGA lover!!!

I invite you to take a look at the new manuals on the web page, and have a tour, Enjoy, and Love FPGAs and Embedded Systems!

Cheers!

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Creating a Shared library using Intel ARM SoC DS IDE and testing it with Python - Linux
Adding tasks to Linux Initialization using inittab - DE0-NANO-SOC

Adding tasks to Linux Initialization using inittab, DE0-NANO-SOC

Adding tasks to Linux Initialization using inittab - DE0-NANO-SOC
Creating a Shared library using Vitis and testing it with Python - Petalinux

In this manual you will learn to create a shared library(.so) for your embedded ARM using Vitis. so you can use on Python on Petalinux.

Creating a Shared library using Vitis and testing it with Python - Petalinux
UART Full Duplex Core - Verilog

Uart Full Duplex Verilog

UART Full Duplex Core - Verilog
PWM Core - Verilog

Motor PWM module, verilog

PWM Core - Verilog
DAC MCP4821 Core - Verilog HDL

This DAC(MCP4821) module was developed by the UPB students Jose Velandia & Henry Lizaro in the year 2012, you can see here the description of the module, plus a very useful application on digital modulations(ASK, FSK, BPSK, QPSK), that you could use to learn more about digital modulations and to visualize at the output of the MCP4821 DAC.

DAC MCP4821 Core - Verilog HDL
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This Qsys component has been designed to be used with the chip Wiznet W5100 alongside the soft-core Nios II. This manual will tell you how to implement it using the DE0-NANO, and C5GX, and is divided into two parts:..

Wiznet 5100 Core
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Signal wave graphing is a common requirement in embedded instrumentation systems dedicated to the monitoring and logging of external variables. However, this functionality requires a lot more resources than the ones available in simple signal acquisition systems as expected in power and economic budgets, as they may require the use of external GPUs that integrate a variety of graphing resources unnecessary for logging-and-graphing dedicated applications, such as Digital Oscilloscopes, Industrial Monitoring, Vital Signs Monitors and others.

Waves Graphing Acceleration using FPGA
X-ISCKER - IPCore

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X-ISCKER - IPCore
N64 Controller Module - DE0-NANO

In this manual you are going to understand how the N64 Controller works, and how we can acquire through a simple Finite State Machine (FSM), all the buttons states from the N64 controller using the DE0-NANO (you can use any FPGA board, and implement this manual).

N64 Controller Module - DE0-NANO
DE0 NANO PlayStation Controller Interface

This manual provides instructions on how to convert your PSx controller's output from the PSx connector to UART. In addition, you will learn how to receive data from the UART and how to emulate keyboard and mouse functions using Python scripting.

DE0 NANO PlayStation Controller Interface
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This Verilog core was designed to control the DAC LTC®LTC2624 which is a quad 12-bit 2.5V to 5.5V rail-to-rail voltage output DACs

DAC LTC2624 core - Verilog HDL
Motor Encoder Core - Verilog

motor encoder verilog

Motor Encoder Core - Verilog
IMPLEMENTATION OF A PID CONTROLLER EMBEDDED IN A FPGA FOR POSITIONING A DC MOTOR

IMPLEMENTATION OF A PID CONTROLLER EMBEDDED IN A FPGA FOR POSITIONING A DC MOTOR

IMPLEMENTATION OF A PID CONTROLLER EMBEDDED IN A FPGA FOR POSITIONING A DC MOTOR
LCD DRIVER(PSP SCREEN) with and without Nios II

PSP screen, 4.3 inch, Touch Screen, Verilog, FPGA, Nios II

LCD DRIVER(PSP SCREEN) with and without Nios II
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HDMI Core on DE0-NANO - Project
Matrix Multiplication and Gaussian Elimination C optimization.

Matrix Multiplication and Gaussian Elimination C optimization.

Matrix Multiplication and Gaussian Elimination C optimization.
Turning On qsys debug messages

Turning On qsys debug messages
Introduction to HLS (High Level Synthesis)

HLS, OpenCL, MyHDL, Heuristics, FPGA, Nios II, Holguer.

Introduction to HLS (High Level Synthesis)
Coding USB-Serial using Android Studio

Coding USB-Serial using Android Studio
Simple Tunnel Working on C

Simple Tunnel Working on C
LFSRs, Cryptology in Python Part 1 - Software

LFSRs, Cryptology, python, FPGA, DE0-NANO

LFSRs, Cryptology in Python Part 1 - Software
PyQT Introduction

PyQT Introduction
Three-Line delay buffers for Image Processing - DE2-115

Line buffers serve as a common tool for data buffering, allowing for the processing of a larger data window. This window is then subdivided into 3x3 pixel kernels, also referred to as neighborhoods. These small regions are typically employed to facilitate the application of digital filters to an image, effectively eliminating superfluous information and thereby simplifying the process of identifying specific features within the image.

Three-Line delay buffers for Image Processing - DE2-115
Build Petalinux for ZCU106 PS and PL based 10G Ethernet

Compile Petalinux for ZCU106 10G Ethernet Example

Build Petalinux for ZCU106 PS and PL based 10G Ethernet
My first project on Zynq using Vivado from Scratch - PYNQ-Z2

My first project on Zynq using Vivado from Scratch - PYNQ-Z2

My first project on Zynq using Vivado from Scratch - PYNQ-Z2
Seeeduino Xiao - HID device to Shutdown Your Friend's Computer.

Emulate the strokes of the keyboard to shutdown your friend's computer. Using Seeeduino Xiao.

Seeeduino Xiao - HID device to Shutdown Your Friend's Computer.
Booting Nios® II from Quad Serial Configuration (EPCQ), Cyclone V GX Starter Kit.

How to boot Nios II on Cyclone V GX Starter Kit

Booting Nios® II from Quad Serial Configuration (EPCQ), Cyclone V GX Starter Kit.
Setting the D5M Terasic Camera using Nios II at 1080p

This manual is composed by two sections: Hardware description part. In this part you can learn how to create a video acquisition system using Qsys. Software part. In this part you will learn how to communicate with the D5M camera using Nios II through the "Audio and Video config" core. D5M Camera, Cyclone V GX, Holguer, 1080p, Verilog

Setting the D5M Terasic Camera using Nios II at 1080p
FreeRTOS(Accelerometer-Vpython) - DE0-NANO

FreeRTOS,Accelerometer, python, C, Nios II, UART

FreeRTOS(Accelerometer-Vpython) - DE0-NANO
PC Engine / Turbografx-16 - DE0-NANO

Based on Gregory Estrade's Work. I have ported the PC Engine System on the DE0-NANO back in 2014, why don't you have a look?, Maybe port it on another FPGA? Here you go the DE0-NANO (Download:Sources) Ready to be Synthesized.

PC Engine / Turbografx-16 - DE0-NANO
Mandelbrot - DE0-NANO

DE0-NANO, Mandelbrot, Nios II, PSX, PSP screen

Mandelbrot - DE0-NANO
WAV Player - DE0-NANO

WAV Player, DE0-NANO, FPGA, Verilog, TFT, LCD, FIFO

WAV Player - DE0-NANO
VGA Retro Sprites and Sound Synthesis - DE0-NANO

VGA Retro Sprites, Sound Synthesis, DE0-NANO, FPGA, Retro

VGA Retro Sprites and Sound Synthesis - DE0-NANO
VGA Retro Game Introduction - DE0-NANO

VGA Retro Game Introduction - DE0-NANO

VGA Retro Game Introduction - DE0-NANO
Bresenham's Algorithm - DE0-NANO-SOC

Bresenham's Algorithm, DE0-NANO-SOC, FPGA, VERILOG

Bresenham's Algorithm - DE0-NANO-SOC
Nios II Software

FPGA, Nios II, DE0-NANO-SOC

Nios II Software
HPS Software - DE0-NANO-SOC

HPS Software - DE0-NANO-SOC

HPS Software - DE0-NANO-SOC
UCOS II - DE0-NANO-SOC

Nios II, UCOSII, OS, FPGA, DE0-NANO

UCOS II - DE0-NANO-SOC
Data Sync - DE0-NANO-SOC

Data Sync - DE0-NANO-SOC
Pipeline - DE0-NANO-SOC

Pipeline - DE0-NANO-SOC

Pipeline - DE0-NANO-SOC
PicoCtrl - DE0-NANO-SOC

PicoCTRL on FPGA

PicoCtrl - DE0-NANO-SOC
HARD PROCESSOR SYSTEM (HPS) - DE0-NANO-SOC

Introduction to HPS SoC

HARD PROCESSOR SYSTEM (HPS) - DE0-NANO-SOC
NCO - DE0-NANO-SOC

NCO - DE0-NANO-SOC
Karplus Strong Software Hardware Co-design - DE0-NANO-SOC

Karplus Strong, DE0-NANO-SOC, FPGA Verilog

Karplus Strong Software Hardware Co-design - DE0-NANO-SOC
DE0-NANO-SOC

DE0-NANO-SOC
1) Getting Started - DE0-NANO-SOC

1) Getting Started - DE0-NANO-SOC
VGA - DE0-NANO-SOC

VGA, DE0-NANO-SOC, FPGA, Verilog

VGA - DE0-NANO-SOC
Nios II Hardware

FPGA, Nios II Hardware, Qsys, Quartus, DE0-NANO-SOC, QAR

Nios II Hardware
Arduino Core - DE0-NANO-SOC

Arduino on FPGA

Arduino Core - DE0-NANO-SOC
Nios II Custom Hardware - DE0-NANO-SOC

Nios II Custom Hardware - DE0-NANO-SOC

Nios II Custom Hardware - DE0-NANO-SOC
FIR Filter Hardware Part 2 - DE0-NANO-SOC

FIR Filter Hardware Part 2 - DE0-NANO-SOC

FIR Filter Hardware Part 2 - DE0-NANO-SOC
Non-volatile - DE0-NANO-SOC

Non-volitle, Nios II, FPGA, DE0-NANO-SOC

Non-volatile - DE0-NANO-SOC
FreeRTOS - DE0-NANO-SOC

FreeRTOS - DE0-NANO-SOC
2) Introduction - DE0-NANO-SOC

Introduction - DE0-NANO-SOC

2) Introduction - DE0-NANO-SOC
FIR Filter Software Part 1 - DE0-NANO-SOC

FIR Filter, FPGA, Signal Processing, Matlab

FIR Filter Software Part 1 - DE0-NANO-SOC
HPS System Console - DE0-NANO-SOC

HPS System Console - DE0-NANO-SOC

HPS System Console - DE0-NANO-SOC
3) Simulation and FSM Design - DE0-NANO-SOC

Simulation and FSM Design - DE0-NANO-SOC

3) Simulation and FSM Design - DE0-NANO-SOC
SNES Controller Module - DE0-NANO-SOC

In this manual you are going to understand how the SNES Controller Works, and how we can acquire through a simple Finite State Machine (FSM), all the buttons states from the SNES controller using the de0-nano SOC (you can use any FPGA borad, and implement this manual).

SNES Controller Module - DE0-NANO-SOC
Nios II Karplus Software Based - DE0-NANO-SOC

Karplus Strong, FPGA, Nios II

Nios II Karplus Software Based - DE0-NANO-SOC
DMA - DE0-NANO-SOC

DMA - DE0-NANO-SOC

DMA - DE0-NANO-SOC
4) IP Catalog - DE0-NANO-SOC

IP Catalog, DE0-NANO-SOC, IEEE754, FPGA, VERILOG

4) IP Catalog - DE0-NANO-SOC

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