Written by Holguer A. Becerra
Based on Gregory Estrade's Work.
I have ported the PC Engine System on the DE0-NANO back in 2014, why don't you have a look?, Maybe port it on another FPGA?
Here you go the DE0-NANO (Download:Sources) Ready to be Synthesized. 
Open the Project, Analyze the project, make your changes, Compile and then program the .sof.
I made some changes on the original project so that you know, which are:
  • Booting the PCengine from EPCS memory instead of using the flash memory of DE1 or DE2-115.
    wire [23:0]FL_ADDR;
    wire [7:0]FL_DQ;
    wire data_rdy;
    wire clk_epcs;
    wire boot_oe_n;
    //EPCS reader
    epcs_reader flash
    	.clk(clk_epcs) ,	// input  clk_sig
    	.start(boot_oe_n) ,	// input  read_clk_sig
    	.Serial(EPCS_ASDO) ,	// output  Serial_sig
    	.address({2'b00,FL_ADDR[21:0]}) ,	// input [23:0] address_sig
    	.serial_byte(EPCS_DATA0) ,	// input  serial_byte_sig
    	.data_out(FL_DQ) ,	// output [7:0] flash_byte_sig
    	.SPI_clock(EPCS_DCLK) ,	// output  SPI_clock_sig
    	.FSM_ENABLE(1'b1) ,	// input  FSM_ENABLE_sig
    	.CS(EPCS_NCSO) 	// output  CS_sig
  • Audio works with Delta Sigma instead of WM8731 codec, ideal for the DE0-NANO.
    assign GPIO[27]=AUDIO_L;
    assign GPIO[29]=AUDIO_R;

  • The VGA Connection is based on the following Schematic
    // VGA Pins
    assign GPIO[0]=vga_R[3];
    assign GPIO[1]=vga_R[2];
    assign GPIO[3]=vga_R[1];
    assign GPIO[5]=vga_R[0];
    assign GPIO[7]=vga_G[3];
    assign GPIO[9]=vga_G[2];
    assign GPIO[11]=vga_G[1];
    assign GPIO[13]=vga_G[0];
    assign GPIO[15]=vga_B[3];
    assign GPIO[17]=vga_B[2];
    assign GPIO[19]=vga_B[1];
    assign GPIO[21]=vga_B[0];
    assign GPIO[23]=V_SYNC;
    assign GPIO[25]=H_SYNC;​
  • In addition, the GPIO of the DE0-NANO
  • For now the system has no controller added, but you could simply add one by following any of the given manuals on:
    For that you should modify the following lines by adding any of the controllers and connecting them to the GPIOs.
    wire UP_CONTROLLER=1'b0;
    wire DOWN_CONTROLLER=1'b0;
    wire LEFT_CONTROLLER=1'b0;
    wire RIGHT_CONTROLLER=1'b0;
    wire SELECT_CONTROLLER=1'b1;
    wire RUN_CONTROLLER=1'b1;
    wire BUTTON1_CONTROLLER=1'b1;
    wire BUTTON2_CONTROLLER=1'b1;

In order to Load the PC Engine ROMS on the EPCS you should follow the following steps:

  1. Connect the DE0-NANO using your USB to power it on.
  2. Run the "DE0_NANO_Control_Panel.exe" program.
  3. Click on "Open", select "Open USB Port 0".
  4. Select the "EPCS" tab, and click on "Chip Erase".
  5. Check "File Length", then click on "Write a File to EPCS".
  6. Choose a PC-Engine ROM(JackieChan.pce). You can fin other ROMS here https://romhustler.org/rom/tg16/ 
  7. Once the write operation is done, close the "DE0-NANO Control Panel".
  • Open Control panel, once opened, click on Memory, then on Memory type list select "EPCS", select the check "File Length", on the address of section Sequential Write  type "07d000" and then click on the button write file to memory.
  • Select the file  JackieChan.pce, and OK.
  • Then wait until the EPCS is written.

    Note: if it does not let you write, first click on Erase "Chip Erase (70 sec)"
The switches(SW[3:1]) depend on the type of pceeng image.
- SW1 : header present or not (usually, ROMs do have this header, so set it to "1").
- SW2 : set it to "1" if your ROM is 768 Kb.
- SW3 : set it to "1" if you're dealing with a TGFX ROM instead of a PCE ROM.
  NEC created a very basic region-lockout by swapping data bits on the cartridge
  and cartridge connector on US (TGFX-16) consoles.
  So, for the (very few) ROMs that have been dumped off a US cartridge, set it to "1".  
  If unsure, set it to "0".
//CONTROL PCEngine Signals
wire RESET = ~KEY[0];
wire ROM_HEADER =SW[1];
wire ROM_SPLIT =SW[2];
wire BITFLIP =SW[3];

Demostration videos:


  Aditionally you can see the PC engine running on a PSP Screen.



For more info you can go to:LCD DRIVER(PSP SCREEN) with and without Nios II


Challenges to be done, that you could do on your own:

  1. Why don't you try to port it on the DE0-NANO-SOC, and use the ARM9 to reprogram the logic of the FPGA, and to load the ROMS?
  2. Do the same using Nios II, or RISC-V.
  3. Port it on the Sipeed TANG PriMER FPGA Dev. Board