In this manual you will learn to create a shared library(.so) for your embedded ARM using Vitis. so you can use on Python on Petalinux.

Adding tasks to Linux Initialization using inittab, DE0-NANO-SOC

This Qsys component has been designed to be used with the chip Wiznet W5100 alongside the soft-core Nios II. This manual will tell you how to implement it using the DE0-NANO, and C5GX, and is divided into two parts:..

Uart Full Duplex Verilog

In this manual you are going to understand how the N64 Controller works, and how we can acquire through a simple Finite State Machine (FSM), all the buttons states from the N64 controller using the DE0-NANO (you can use any FPGA board, and implement this manual).

Computer Architecture embraces all three aspects of a processor design: instruction set, functional estructure and hardware implementation. The main architectures are RISC (Reduced Instruction Set Computing) and CISC (Complex Instruction Set Computing) which led to x86 as we still recognize now. Both designs bring electronics or computer science students the basic concepts they should learn. Therefore, this project brings an opportunity to learn this basic concepts through the HDL description in Verilog of two processors (One for each architecture) implemented on FPGA devices, together with strong documentation, common assembly language instructions and support software.

Signal wave graphing is a common requirement in embedded instrumentation systems dedicated to the monitoring and logging of external variables. However, this functionality requires a lot more resources than the ones available in simple signal acquisition systems as expected in power and economic budgets, as they may require the use of external GPUs that integrate a variety of graphing resources unnecessary for logging-and-graphing dedicated applications, such as Digital Oscilloscopes, Industrial Monitoring, Vital Signs Monitors and others.

In this practice, we will understand HDMI (High Definition Multimedia Interface) video interface built for the DE0-NANO. To do this, we must understand how TMDS (Transition Minimized Differential Signaling) transmission works and develop a Verilog HDL transmission module capable of controlling this type of video interface using the DE0-NANO (Cyclone IV).

Line buffers serve as a common tool for data buffering, allowing for the processing of a larger data window. This window is then subdivided into 3x3 pixel kernels, also referred to as neighborhoods. These small regions are typically employed to facilitate the application of digital filters to an image, effectively eliminating superfluous information and thereby simplifying the process of identifying specific features within the image.

My first project on Zynq using Vivado from Scratch - PYNQ-Z2

How to boot Nios II on Cyclone V GX Starter Kit

DE0-NANO, Mandelbrot, Nios II, PSX, PSP screen

VGA Retro Sprites, Sound Synthesis, DE0-NANO, FPGA, Retro

WAV Player, DE0-NANO, FPGA, Verilog, TFT, LCD, FIFO

FPGA, Nios II, DE0-NANO-SOC

DMA - DE0-NANO-SOC

Non-volitle, Nios II, FPGA, DE0-NANO-SOC

Introduction - DE0-NANO-SOC

HPS System Console - DE0-NANO-SOC

Simulation and FSM Design - DE0-NANO-SOC

PicoCTRL on FPGA

Karplus Strong, DE0-NANO-SOC, FPGA Verilog

FIR Filter, FPGA, Signal Processing, Matlab