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In this manual you will learn to create a shared library(.so) for your embedded Intel ARM SoC using ARM Development Studio IDE . so you can use on Python on your Linux on you Intel ARM SoC.

This DAC(MCP4821) module was developed by the UPB students Jose Velandia & Henry Lizaro in the year 2012, you can see here the description of the module, plus a very useful application on digital modulations(ASK, FSK, BPSK, QPSK), that you could use to learn more about digital modulations and to visualize at the output of the MCP4821 DAC.

Computer Architecture embraces all three aspects of a processor design: instruction set, functional estructure and hardware implementation. The main architectures are RISC (Reduced Instruction Set Computing) and CISC (Complex Instruction Set Computing) which led to x86 as we still recognize now. Both designs bring electronics or computer science students the basic concepts they should learn. Therefore, this project brings an opportunity to learn this basic concepts through the HDL description in Verilog of two processors (One for each architecture) implemented on FPGA devices, together with strong documentation, common assembly language instructions and support software.

motor encoder verilog

Signal wave graphing is a common requirement in embedded instrumentation systems dedicated to the monitoring and logging of external variables. However, this functionality requires a lot more resources than the ones available in simple signal acquisition systems as expected in power and economic budgets, as they may require the use of external GPUs that integrate a variety of graphing resources unnecessary for logging-and-graphing dedicated applications, such as Digital Oscilloscopes, Industrial Monitoring, Vital Signs Monitors and others.

Uart Full Duplex Verilog

In this practice, we will understand HDMI (High Definition Multimedia Interface) video interface built for the DE0-NANO. To do this, we must understand how TMDS (Transition Minimized Differential Signaling) transmission works and develop a Verilog HDL transmission module capable of controlling this type of video interface using the DE0-NANO (Cyclone IV).

IMPLEMENTATION OF A PID CONTROLLER EMBEDDED IN A FPGA FOR POSITIONING A DC MOTOR

Matrix Multiplication and Gaussian Elimination C optimization.

HLS, OpenCL, MyHDL, Heuristics, FPGA, Nios II, Holguer.

LFSRs, Cryptology, python, FPGA, DE0-NANO

Compile Petalinux for ZCU106 10G Ethernet Example

Emulate the strokes of the keyboard to shutdown your friend's computer. Using Seeeduino Xiao.

This manual is composed by two sections: Hardware description part. In this part you can learn how to create a video acquisition system using Qsys. Software part. In this part you will learn how to communicate with the D5M camera using Nios II through the "Audio and Video config" core. D5M Camera, Cyclone V GX, Holguer, 1080p, Verilog

VGA Retro Game Introduction - DE0-NANO

VGA Retro Sprites, Sound Synthesis, DE0-NANO, FPGA, Retro

WAV Player, DE0-NANO, FPGA, Verilog, TFT, LCD, FIFO

Arduino on FPGA

Bresenham's Algorithm, DE0-NANO-SOC, FPGA, VERILOG

VGA, DE0-NANO-SOC, FPGA, Verilog

Karplus Strong, DE0-NANO-SOC, FPGA Verilog

FIR Filter Hardware Part 2 - DE0-NANO-SOC

In this manual you are going to understand how the SNES Controller Works, and how we can acquire through a simple Finite State Machine (FSM), all the buttons states from the SNES controller using the de0-nano SOC (you can use any FPGA borad, and implement this manual).

HPS System Console - DE0-NANO-SOC

Nios II, UCOSII, OS, FPGA, DE0-NANO

FPGA, Nios II Hardware, Qsys, Quartus, DE0-NANO-SOC, QAR

Pipeline - DE0-NANO-SOC