module tx_control_to_pc(clk,
	l1,
	l2,
	r1,
	r2,
	l3,
	r3,
	d_pad_up,
	d_pad_down,
	d_pad_left,
	d_pad_right,
	square,
	triangle,
	circle,
	x,
	select,
	start,
	left_analog_up_down,
	left_analog_right_left,
	right_analog_up_down,
	right_analog_right_left,
	Tx_to_pc);

	
input	clk; // 50Mhz
input	l1;
input	l2;
input	r1;
input	r2;
input l3;
input r3;
input	d_pad_up;
input	d_pad_down;
input	d_pad_left;
input	d_pad_right;
input	square;
input	triangle;
input	circle;
input	x;
input	select;
input	start;
input	[7:0]left_analog_up_down;
input	[7:0]left_analog_right_left;
input	[7:0]right_analog_up_down;
input	[7:0]right_analog_right_left;
output Tx_to_pc;

parameter SIZE_PKG1=3'd4;
parameter SIZE_PKG2=3'd6;

//							load_data, count_pack, reset_count, toggle_pack, send_data__ state
parameter IDLE= 	   {1'b0,		1'b0,		1'b1,			1'b0, 			1'b0, 	3'b000};
parameter SECOND=		{1'b1,		1'b0,		1'b0,			1'b0, 			1'b0, 	3'b001};
parameter THIRD=		{1'b0,		1'b0,		1'b0,			1'b0, 			1'b1, 	3'b010};
parameter FOURTH=		{1'b0,		1'b1,		1'b0,			1'b0, 			1'b0, 	3'b011};
parameter FIFTH=		{1'b0,		1'b0,		1'b0,			1'b1, 			1'b0, 	3'b100};


reg [7:0]STATE=IDLE;

wire load_data=STATE[7];
wire next_count=STATE[6];
wire reset_count=STATE[5];
wire toggle=STATE[4];
wire send_byte=STATE[3];


wire busy_tx;

// Paquete de datos # 1
wire [7:0]packets1[4:0];
wire [7:0]checksum1 =(packets1[0][7:0]+packets1[1][7:0]+packets1[2][7:0]+packets1[3][7:0]);

// Paquete de datos # 2
wire [7:0]packets2[6:0];
wire [7:0]checksum2 =(packets2[0][7:0]+packets2[1][7:0]+packets2[2][7:0]+packets2[3][7:0]+packets2[4][7:0]+packets2[5][7:0]);

// Paquete de datos # 1 - codificacion
assign packets1[0][7:0]=8'd17;// ID
assign packets1[1][7:0]={1'b1,2'd0,l3,r3,2'd0,checksum1[7]}; // HEAD
assign packets1[2][7:0]={1'b1,l1,l2,r1,r2,select,start,x}; // DATA1
assign packets1[3][7:0]={1'b1,d_pad_up,d_pad_down,d_pad_left,d_pad_right,square,triangle,circle}; // DATA2
assign packets1[4][7:0]={1'b1,(checksum1[6:0])}; // CHECKSUM

// Paquete de datos # 2 - codificacion
assign packets2[0][7:0]=8'd27;// ID
assign packets2[1][7:0]={1'b1,2'd0,right_analog_right_left[7],right_analog_up_down[7],left_analog_right_left[7],left_analog_up_down[7],checksum2[7]}; // HEAD
assign packets2[2][7:0]={1'b1,left_analog_up_down[6:0]}; // DATA1
assign packets2[3][7:0]={1'b1,left_analog_right_left[6:0]}; // DATA2
assign packets2[4][7:0]={1'b1,right_analog_up_down[6:0]}; // DATA3
assign packets2[5][7:0]={1'b1,right_analog_right_left[6:0]}; // DATA4
assign packets2[6][7:0]={1'b1,(checksum2[6:0])}; // CHECKSUM

// Selector de paquetes
reg toggle_reg=1'b0;
reg [2:0]count_packet=3'd0;
reg [7:0]data_to_send_buffer1[4:0];
reg [7:0]data_to_send_buffer2[6:0];

wire [2:0]count_up=toggle_reg ? SIZE_PKG1: SIZE_PKG2;
wire [7:0]data_to_send= toggle_reg ? data_to_send_buffer1[count_packet][7:0]: data_to_send_buffer2[count_packet][7:0];

always@(posedge toggle)
begin
	toggle_reg<=~toggle_reg;
end

always@(posedge next_count, posedge reset_count)
begin
	if(reset_count) count_packet<=3'd0;
	else count_packet<=count_packet+1'b1;
end

always@(posedge load_data)
begin
	if(toggle_reg)
	begin
		data_to_send_buffer1[0][7:0]<=packets1[0][7:0];
		data_to_send_buffer1[1][7:0]<=packets1[1][7:0];
		data_to_send_buffer1[2][7:0]<=packets1[2][7:0];
		data_to_send_buffer1[3][7:0]<=packets1[3][7:0];
		data_to_send_buffer1[4][7:0]<=packets1[4][7:0];
	end
end


always@(posedge load_data)
begin
	if(!toggle_reg)
	begin
		data_to_send_buffer2[0][7:0]<=packets2[0][7:0];
		data_to_send_buffer2[1][7:0]<=packets2[1][7:0];
		data_to_send_buffer2[2][7:0]<=packets2[2][7:0];
		data_to_send_buffer2[3][7:0]<=packets2[3][7:0];
		data_to_send_buffer2[4][7:0]<=packets2[4][7:0];
		data_to_send_buffer2[5][7:0]<=packets2[5][7:0];
		data_to_send_buffer2[6][7:0]<=packets2[6][7:0];
	end
end

always@(posedge clk)
begin
	case(STATE)
	// STAND BY
	IDLE: if(busy_tx) STATE<=IDLE;
			else STATE<=SECOND;
	//LOAD_DATA_IN BUFFER 1 or 2
	SECOND:
			 STATE<=THIRD;
	// SEND BYTE		 
	THIRD:if(busy_tx) STATE<=THIRD;
			else STATE<=FOURTH;
	// Cuente uno en el paquete	
	FOURTH:if(busy_tx) STATE<=FOURTH;
			 else if(count_packet<=count_up) STATE<=SECOND;
			 else STATE<=FIFTH;
	// ir al inicio	
	FIFTH: STATE<=IDLE;
	
	default: STATE<=IDLE;
	
	endcase
end



UART_FullDuplex UART_FullDuplex_inst 
(
	.clk(clk) ,	// input  clk_sig
	.Tx_Start(send_byte) ,	// input  Tx_Start_sig
	.Tx_Data(data_to_send) ,	// input [7:0] Tx_Data_sig
	.Tx(Tx_to_pc) ,	// output  Tx_sig
	.TxD_Busy(busy_tx) ,	// output  TxD_Busy_sig
	.Rx() ,	// input  Rx_sig
	.Rx_Data() ,	// output [7:0] Rx_Data_sig
	.RxD_Ready() 	// output  RxD_Ready_sig
);


endmodule