`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: Semillero ADT - UPB Bucaramanga // Engineer: Holguer A Becerra Daza // // Create Date: 20:32:24 05/10/2012 // Design Name: // Module Name: SPI_SLAVE // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module SPI_SLAVE(CLK_50Mhz,CS,MOSI,SCK,DataIn,Start_in,Finish_out); /*---SIGNALS-------#-STATE*/ /*FINISH__UP_SCK__CS STATE*/ parameter IDLE= 7'b1______0___0___1__000; parameter FIRST= 7'b0______0___0___0__001; parameter SECOND= 7'b0______0___1___0__010; parameter THIRD= 7'b0______1___0___0__011; parameter FOURTH= 7'b0______0___0___1__100; input CLK_50Mhz; input [31:0]DataIn; input Start_in; output CS; output MOSI; output SCK; output Finish_out; reg [6:0]STATE_SPI=IDLE; reg [5:0]Count_data=6'd0; wire Finish=STATE_SPI[6]; wire UP_Count=STATE_SPI[5]; wire SCK_OUT=STATE_SPI[4]; wire CS_OUT=STATE_SPI[3]; wire Reset_count=STATE_SPI[3]; assign Finish_out=Finish; assign CS=CS_OUT; assign SCK=SCK_OUT; assign MOSI=DataIn[31-Count_data]; always@(posedge UP_Count,posedge Reset_count) begin if(Reset_count) Count_data<=6'd0; else Count_data<=Count_data+1'b1; end always@(posedge CLK_50Mhz) begin case(STATE_SPI) IDLE: begin if(Start_in==1'b1) STATE_SPI<=FIRST; else STATE_SPI<=IDLE; end FIRST: STATE_SPI<=SECOND; SECOND: STATE_SPI<=THIRD; THIRD: begin if(Count_data<32) STATE_SPI<=FIRST; else STATE_SPI<=FOURTH; end FOURTH: STATE_SPI<=IDLE; endcase end endmodule