`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    18:31:09 06/04/2009 
// Design Name:    Jose Pablo Pinilla & Holguer A Becerra
// Module Name:    PWM 
// Project Name:   
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision:  
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////

module PWM #(parameter Bits_counter = 7, Periodo=3'd7)
	 (	input  clk, output motor, input  [Bits_counter-1:0] duty_cycle);	
   
   reg [Bits_counter-1:0] Timer1=0;
   reg PWM_OUTPUT;
	
	assign motor = PWM_OUTPUT; 
	
   always @(posedge clk)
	begin
		if (Timer1 >= Periodo)
			begin
					Timer1 <= 0;
					PWM_OUTPUT<=PWM_OUTPUT;
			end		
		else
		   begin
				  Timer1 <= Timer1+1; 
				  if (Timer1 >= duty_cycle)
						 PWM_OUTPUT<=1'b0;
				  else 
						PWM_OUTPUT <= 1'b1;		  
		   end
	end	
	
endmodule