system | system
1.0 |
2014.03.09.23:38:10 | Generation Report |
Output Directory | C:/FPGAs/DE0_NANO_SD_card/ | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Files | C:/FPGAs/DE0_NANO_SD_card/system/synthesis/system.v (557216 bytes VERILOG)
C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_cpu.sdc (3625 bytes SDC) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_cpu.v (191895 bytes VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v (6987 bytes VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v (8249 bytes VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v (10055 bytes VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_cpu_ociram_default_contents.mif (5878 bytes MIF) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_cpu_oci_test_bench.v (1454 bytes VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_cpu_rf_ram_a.mif (600 bytes MIF) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_cpu_rf_ram_b.mif (600 bytes MIF) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_cpu_test_bench.v (30028 bytes VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_sdram.v (24301 bytes VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_sysid.v (1445 bytes VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_timer_0.v (6908 bytes VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_uart_0.v (35151 bytes VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_uart_0_input_data_mutex.dat (3 bytes OTHER) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_uart_0_input_data_stream.dat (7 bytes OTHER) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_uart_0_log_module.txt (0 bytes OTHER) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_pio_led_green.v (2478 bytes VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_pio_sw.v (1897 bytes VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/spi_master_if.vhd (5536 bytes VHDL) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/spi_master_core.vhd (11562 bytes VHDL) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_epcs.v (16712 bytes VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_epcs_boot_rom_synth.hex (5148 bytes HEX) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_jtag_uart.v (23607 bytes VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_jtag_uart_input_mutex.dat (3 bytes OTHER) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_jtag_uart_input_stream.dat (10 bytes OTHER) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_jtag_uart_output_stream.dat (0 bytes OTHER) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/altera_merlin_master_translator.sv (16415 bytes SYSTEM_VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/altera_merlin_slave_translator.sv (15976 bytes SYSTEM_VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/altera_merlin_master_agent.sv (8662 bytes SYSTEM_VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/altera_merlin_slave_agent.sv (17560 bytes SYSTEM_VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv (10392 bytes SYSTEM_VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/altera_avalon_sc_fifo.v (32198 bytes VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_addr_router.sv (6628 bytes SYSTEM_VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_addr_router_001.sv (8608 bytes SYSTEM_VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_id_router.sv (5895 bytes SYSTEM_VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_id_router_001.sv (5907 bytes SYSTEM_VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_id_router_003.sv (5826 bytes SYSTEM_VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/altera_merlin_traffic_limiter.sv (13743 bytes SYSTEM_VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/altera_avalon_st_pipeline_base.v (4716 bytes VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/altera_merlin_burst_adapter.sv (36989 bytes SYSTEM_VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/altera_reset_controller.v (3592 bytes VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/altera_reset_synchronizer.v (3564 bytes VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/altera_reset_controller.sdc (1179 bytes SDC) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_cmd_xbar_demux.sv (4740 bytes SYSTEM_VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_cmd_xbar_demux_001.sv (9188 bytes SYSTEM_VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/altera_merlin_arbitrator.sv (9448 bytes SYSTEM_VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_cmd_xbar_mux.sv (11015 bytes SYSTEM_VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_rsp_xbar_demux.sv (4106 bytes SYSTEM_VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_rsp_xbar_demux_003.sv (3480 bytes SYSTEM_VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_rsp_xbar_mux.sv (13059 bytes SYSTEM_VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_rsp_xbar_mux_001.sv (19012 bytes SYSTEM_VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/altera_merlin_width_adapter.sv (36187 bytes SYSTEM_VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/altera_avalon_st_pipeline_stage.sv (5195 bytes SYSTEM_VERILOG) C:/FPGAs/DE0_NANO_SD_card/system/synthesis/submodules/system_irq_mapper.sv (1907 bytes SYSTEM_VERILOG) |
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Instantiations |
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