module multi(
	input [3:0]in,
	input start,
	input clk,
	output idle,
	output finish,
	output [7:0]salida
);
                 //finish___idle____state
localparam IDLE   = 6'b0_____1_____0001;
localparam STATE1 = 6'b0_____0_____0010;
localparam STATE2 = 6'b0_____0_____0100;
localparam FINISH = 6'b1_____0_____1000;

reg [5:0]state=IDLE;
reg [7:0]a=8'd0;
reg [7:0]salida1=8'd0;
assign salida[7:0]=salida1[7:0];
assign finish=state[5];
assign idle=state[4];

always@(posedge clk)
begin
	case(state[5:0])
	IDLE:
	begin
		a[7:0]<=in[3:0];
		state[5:0]<=STATE1;
		if(!start)
		begin
			state[9:0]<=IDLE;
		end
	
	end
	STATE1:
	begin
		a[7:0]<=a[7:0]*3;
		state[5:0]<=STATE2;
	end
	
	STATE2:
	begin
		a[7:0]<=a[7:0]+3;
		state[5:0]<=FINISH;
	end
	
	FINISH:
	begin
		a[7:0]<=a[7:0];
		state[5:0]<=IDLE;
	end
	
	default:
	begin
		a[7:0]<=a[7:0];
		state[5:0]<=IDLE;
	end
	
	endcase

end
always@(posedge finish)
begin
	salida1[7:0]<=a[7:0];
end



endmodule