Author:  Edgar Rodrigo Mancipe Toloza

 

Downloadables: 

• Quartus Project DE0-NANO
• Verilog Modules
  

 

ABSTRACT: The main objective of this paper is to present the steps of how to program a PID controller in a FPGA, and in that way to control a DC motor using Pulse Width Modulation. Also we want to give some ideas to people interested in program embedded controllers in hardware.

During the project we will use some tools to help us to visualize the behavior of the controller on the computer screen through rs232 communication and LabView chart to plot, and LCD display for visualize the Set Point, gains and the current value.

 

KEYWORDS: PID, Control, FPGA, DE0-Nano, Embedded.

 

INTRODUCTION

 

Nowadays FPGA's have increased their popularity due the many ways to acquire it, reliability, and low costs. As a consequence of that, we can see more FPGA's applications in control systems.

For many years, microcontrollers used to be on the top of this field due their low-cost, but through years FPGA's have turned into a striking option, thanks to its main property of controlling many systems in parallel in the same embedded system.[1]. 

In this project we want to show in a quick way, how to program a PID control in FPGA using Verilog language, also we will change the values of Gain variables to see the behavior of the controlled value.

This article is not intended to give a definitive PID algorithm, the intention is to introduce and give some ideas for the readers of how to create and implement their own PID equation embedded in FPGA.

 

 MATERIALS 

This section will show the name of the main objects used in the analog and digital interface of the project for signal conditioning and power circuit.

• DE0-NANO BOARD: The development board selected for this Project is the DE0-Nano, which contains the following characteristics: [2]
  • Altera FPGA Cyclone IV EP4CE22F17C6
  • Analog-to-digital converter ADC128S022
  • Configuration device EPCS16 for non-volatile data storage
  • 4 dip-switch
  • 2 push buttons
  • 8 LED's
    
    

    Figure 1. DE0-Nano Board.

• GEARMOTOR: The gearmotor selected have the next characteristics:

  • Torque 18Kg*cm
  • 80RPM
  • Power supply 12Vdc
    • Quadrature encoder of 8384 pulses per round 3v.
      
      
      
      
      

      Figure 2. Gearmotor. [3]

      
      
      

• DISPLAY HD44780 2x16:  Monochromatic display 2X16 that will be use to visualize de set-point, current variable, proportional, integral and derivative gain
  
  

  Figure 3. LCD 2x16. [4]

• H BRIDGE: the control circuit and power circuit, a L293D H Bridge is the selected option, so in that way the control circuit send digital signals to the chip for select the rotation of the motor. [5]
  

  Figure 4. L293D Block Diagram.

• SERIAL-TO-USB CONVERTER:  For visualize the behavior of the variables in the computer screen, we decided to use a serial-to-usb FTDI FT232RL converter. So through a serial RS232 algorithm coming from the embedded we can send the information of the data's. [6]
  

  Figure 5. Serial-to-USB converter FT232RL.

 

BLOCK  DIAGRAM OF THE CONTROLLER

Before start to program the FPGA, is necessary defining a strategy through a block diagram. In the Figure 6, we can see that the Set Point is selected using a Dip- switch and the feedback signal is coming from the quadrature encoder coupled to the DC motor. The error is the difference between Set Point and feedback (Encoder), and the error sign defines the rotation of the motor through the H Bridge. A Pulse Width Modulation (PWM) is the output signal of the PID algorithm that will change its Duty Cycle depending of the controller result.

 

Figure 6 Block Diagram of the controller.

 

PROGRAMMING

Once defined the strategy for the controller, we proceed to program the algorithm in HDL Verilog, using Quartus II. In this case we divided the entire Project in different sub-modules that will allow us to interpret and design in modular way, so that is going to be an advantage at the moment of write and understand the program lines

 

• SET POINT:
  For the Set Point there are 5 predefined positions that will be selected through a dip-switch. Due that the encoder coupled to the gearmotor generates 8384 pulses per round is necessary to calculate the value for each position
  
  
  
  

  Once we have the number of pulses for each position of the motor we proceed to program the set point selector, the next image will show the SP program:

  
  

  Algorithm for the Set Point.

• CURRENT VALUE

  For know the value of the current value is necessary to read and interpret the data received by the encoder coupled to the DC motor. So in that case we use a circuit that will allow us to interpret the 2 quadratures signals into a counter that increment and decrement its value depending of the rotation of the encoder. [7]
  

  Figure 8. Quadrature decoder coupler circuit.

   

  In the figure 8 we can see that the count direction will determine if the counter will ascend or descend, also the count enable will be the clock pulse that determines the moment to calculate.

  The interpretation of this circuit in Verilog is shown in Figure 9.
  

  Figure 9. Verilog algorithm for quadrature decoder coupler circuit.
  
  

• ERROR SIGNAL

  The error signal is calculated with the difference between Set Point and Feedback as we can see in algorithm shown in the figure 10.
  

  Figure 10. Verilog algorithm for error.
  
  

  But it's important to take note that when the feedback value is bigger than set-point value, it will be a negative saturation so it's necessary to identify when this happen with a signed bit, also put a condition if the signed bit tells that the value it's negative, do a two's complement. The next figure shows a possible way to do that: [8]
  
  

  Verilog algorithm for two's complement.
  
  

• CONTROL

  Before start to write the control algorithm was necessary to define the expression to use, in this case we consulted the incremental PID algorithm as shown in the next equation: [9]
  
  After that we proceed to program the equation using a Finite State Machine (FSM) using each state for doing a operation, and add and substract at the end, as shown in the next figure:
  
  Figure 12. Verilog algorithm for PID controller
  
  

  Another important aspect to have in account is the anti-windup, due the abrupt change of the set point, the control signal can saturate into a max value or a min value (0-64000 on this case), in order to avoid that, an anti- windup algorithm is necessary, a possible way to describe that algorithm is shown in the next figure:
  
  
  Figure 13. Verilog algorithm for Anti-windup
  
  

• PWM

  As we saw in figure 6, a PWM signal is going to be associated to the controller, so the duty cycle of the signal will change according to the value of m(k) that is the result of the PID equation. Before writing an algorithm for a PWM signal, it's necessary to think on how it works for an analog PMW circuit, a voltage comparator between a DC voltage level and a ramp wave, as we can see in the figure 14.
  

  Figure 14. Voltage comparator.

  Using that concept, an algorithm is written with a counter as a ramp wave, and the DC level will be the output of the control equation, giving as a result a PWM.

  

  Figure 15. PWM algorithm.

• ROTATION

  The rotation is given by the signal bit coming from the error acquisition, depending of this value the PWM signal will be assigned to one of the two controls pins of the H Bridge. A hysteresis is added when the error is close to zero in order to avoid oscillations.
  
  Figure 16. Rotation algorithm

 

IMPLEMENTATION

On this stage we will present a test of the algorithm performance using labview and RS232 communication to send the data to the pc. Due that the importance of this document it's to present the controller, we are not going to focus in the RS232 algorithm that is also embedded in the FPGA. Another document will present the steps of how to use and program a serial-USB converter FT232.

 

• TEST 1
  

  Parameters:

  • Input: Step
  • Set Point: 180° Set Point: 180
  • Kp=5
  • Ki=0
  • Kd=0

  In figure 17 we can see a higher position error, when Ki is 0, and Kp is very low.
  
  

  Figure 17. Response of test 1.

• TEST 2

  When we raise Kp, we get closer to the desired value (180°), also the controller is faster, but is not the set point reached yet, is shown in figure 18.

  Parameters:

  • Input: Step
  • Set Point: 180° Set Point: 180
  • Kp=10
  • Ki=0
  • Kd=0.
    
    
    
    

    Figure 18. Response of test 2.

• TEST 3

  Parameters:

  • Input: Step
  • Set Point: 180° Set Point: 180
  • Kp=5
  • Ki=3
  • Kd=0

Now we decrease Kp to 5 again, but this time Kp have a different value than 0. In figure 19 we can see that the response tents to reach the set point value slowly but with a small amount of overshoot (less than 5%).

Figure 19. Response of test 3.

 

• TEST 4

  Parameters:

  • Input: Step
  • Set Point: 180° Set Point: 180
  • Kp=10
  • Ki=3
  • Kd=0

Increasing the Kp value will make the response faster, but also will increase the overshoot, as shown in figure 20.

Figure 20. Response of test 4.

• TEST 5

  Parameters:

  • Input: Step
  • Set Point: 180° Set Point: 180
  • Kp=10
  • Ki=17
  • Kd=0

In this case we can see that increasing the Ki value to high, will make oscillate the system before stabilize, figure 21 is the result of the test 5.

Figure 21. Response of test 5.

ASSEMBLY IMAGES

 

Figure 22. Complete project.

 

LCD with Current Variable, Set-Point, Proportional Gain, Integral Gain and Derivative Gain values.

 

Figure 24. Serial-USB converter.

 

CONCLUSION

 

In this project we saw that is viable the implementation of a PID controller in a FPGA, and the modular design allow us to think and solve one problem at once. Trough the test made to the controller we manage to saw the behavior of the controlled variable when we change the values of the proportional an integral gains, as we saw, the proportional gain will give more speed to the controller but it also can increase the overshoot percent, in other way the integral gain can give a more accurate response getting closer to the set-point. There were also a test changing the derivative gain, however the response was always saturated because of the noise derived, so still pending the implementation of an additional filter to solve this problem

 

VIDEO DEMOSTRATION

 

REFERENCES

 

• Allen Interfacing a DC Motor with an FPGA. Terasic Technologies. Aug 10 , 2011
• Terasic Technologies. DE0-Nano Board. DE0-Nano Development and Education Board [Online]. Available: http://www.terasic.com.tw/
• Gearmotor, [Online].                        Available: http://www.dynamoelectronics.com/components/com_virtue mart/shop_image/product/Motoreductor_18K_4c73f49babdc png
• LCD monochromatic      display,      [Online].      Available http://www.dynamoelectronics.com/components/com_virtue mart/shop_image/product/04-03- 02%20LCD%2016x2%20green.jpg
• SGS-Thomson L293D Datasheet. [Online].Available: www.datasheetcatalog.com
• FT232RL. Datasheet. [Online]. Available: http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf
• Jean P. Nicolle. Quadrature Decoder. Feb. 13 2008. [Online]. Available: http://www.fpga4fun.com/QuadratureDecoder.html
• Twos Complement      Numbers      [Online].      Available: http://www.vb-helper.com/tutorial_twos_complement.html
• Antonio Practical PID control. Springer-Verlag London Limited 2006
• BUSO, Simone and MATTAVELLI, Digital Control in Power Electronics. Morgan & Claypool, 2006, pp. 13-31.