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Written by Holguer Andres
 
 
Welcome to FPGA lover!!!
 
Currently, I am moving all my web courses to a single one(www.fpgalover.com) using solely Terasic/Altera Boards. This Web page will have soon all my tutorials including the content of all my courses among I have:
 
 
While this is done, please I invite you to take a look at the new manuals on the web page, and have a tour, Enjoy, and Love FPGAs!
 
PS: Register to get access to exclusive tutorials and manuals.
 
Best Regards.
 
 

Thursday, 23 November 2017

Written by Fabio Andres     In this manual you are going to understand how the SNES Controller Works, and how we can acquire through a simple Finite State Machine (FSM), all the buttons states from the SNES controller using the de0-nano SOC (you can use any FPGA borad, and implement this manual). It is important to make clear that this manual is based on "SNES timing diagram"(Design Methodology) by Thomas D.   Required Materials: Any FPGA board (Though for this manual we...

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Thursday, 23 November 2017

Written by Ernesto Andrés Rincón Cruz Nios® II is an softcore 32-bit processor developed by Altera to be implemented over all Altera (INTEL) FPGA and SoC families.  Some NIOS-II features: No license required. Use fewer than 700 logic elements. 6-stage pipeline runnning up to 30 DMIPS at 175 MHz in Nios II /e "economy" processor (Dhrystones 2.1 benchmark). Deterministic and jitter free real-time performance. Vector Interrupt Controller. Custom instructions (ability...

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Thursday, 23 November 2017

Written by Holguer Andres   Introduction to HLS (High Level Synthesis) Using Verilog, or VHDL as a hardware description language might be difficult for software centric people who have to break the mental paradigm between concurrent software, and concurrent hardware, which sometimes can be confusing, and could be a pain in the ass for many. In addition, while designing a product, or developing a new prototype, using Verilog, or VHDL can be rigorous and tedious, due to the required time...

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Thursday, 23 November 2017

Written by Holguer Andres   W5100 Qsys Component.   This Qsys component has been designed to be used with the chip Wiznet W5100 alongside the soft-core Nios II. This manual will tell you how to implement it using the DE0-NANO, and C5GX, and is divided into two parts: Hardware Part. Quartus Project. Qsys. PINOUT Connections. Software Implementation. WebServer Example. Requirements W5100 module. Option 1(Tested). Option 2(Tested). DE0-NANO (Not to be...

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Thursday, 23 November 2017

  Written by Holguer Andres Requirements: DE0-NANO-SOC with and SD-CARD preloaded with the following Linux Image (compiled and customized by Holguer Andres). Putty.  Procedure: Using putty open the Linux Terminal through the UART port at 115200 bps. On the Console type: nano /etc/inittab​ As you can observe in the next image, and highlighted in red, all the initial system processes init with ":sysinit:" and next to this a command or a script that is going to...

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Thursday, 23 November 2017

  Written by Holguer Andres   In this manual you are going to understand how the N64 Controller works, and how we can acquire through a simple Finite State Machine (FSM), all the buttons states from the N64 controller using the DE0-NANO (you can use any FPGA board, and implement this manual). it is important to make clear that this manual is based on http://larsivar.com/wp/?p=86 manual in which it is explained the N64 controller protocol, there is a software example for acquiring the...

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Thursday, 23 November 2017

How you can turn on debug messages on Qsys If you have already created a qsys file, just follow the next steps Close the <>.qsys file you are working with. Open the file called <preferences.xml>, which is in the folder where your <>.qsys file is. Look for a line with  Replace the line with  Reopen the <>.qsys file you are working with, and you must see on the loading console some new messages which look like these (green bugs):

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Thursday, 23 November 2017

  Setting the D5M Terasic Camera using Nios II at 1920x1080 Written by Holguer Andres Requirements: Quartus Version Above or equal to 14.1 D5M Camera. RAM (Where we can store the video acquisition). HDMI/VGA/SDI, or others video outputs (to stream out the video in order to see the results). This manual is composed by two sections: Hardware description part.In this part you can learn how to create a video acquisition system using Qsys. Software part.In this part you will learn...

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Thursday, 23 November 2017

Written by Juan David   Introducción  El proyecto FPGArduino consiste en transformar el uso que normalmente se le da a la FPGA y usarlo como un sistema de micro controladores programables usando Arduino. El sistema consiste en construir una “CPU CORE” que ejecuta subgrupos de cualquier RISC-V o MIPS grupo de instrucciones.   ¿Qué es softcore? Es un microprocesador de núcleo que puede ser implementado en su totalidad mediante la síntesis de la lógica. Se puede...

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Thursday, 23 November 2017

Written by Fabio Andres   NIOS II PROCESSOR - Hardware Nios II is an embed processor of structure of 32 bits specifically designed for FPGAs of the brand Altera (Intel).  Nios II has many improvements with the original architecture niosll/e, therefore is more suitable for a huge kinds of informatics applications such as DSP and control systems, moreover, Nios II processor is the world's most versatile processor, according to Gartner Research, and is the most widely used soft processor...

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Thursday, 23 November 2017

Written by Sherneyko Plata Rangel Introducción: El procesamiento digital de señales, y en este  caso, el de audio, es una tarea exigente en cuanto a recursos y velocidad,desde sus inicios se han usado  integrados especializados para esta tarea, sin embargo  con los avances de las ultimas décadas dispositivos programables han  adquirido las capacidades para  realizar  estos procesos, entre ellos se  encuentra la   FPGA, que por sus capacidades y estructura pueden...

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Thursday, 23 November 2017

Written by Holguer Andres             Download Sources for Quartus II: Plantilla para la DE0-NANO Binary (*.sof): Descargar Interesting links: https://sites.google.com/site/tecnicasdigitales22012/proyecto-final http://www.gamesx.com/controldata/psxcont/psxcont.htm http://www.billporter.info/playstation-2-controller-arduino-library-v1-0/   If you want to transform your psx controller to uart using your DE0-NANO, download the next...

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Thursday, 23 November 2017

  Written by Holguer Andres   Materiales: DE0-NANO. 4.3inch-480x272-Touch-LCD.   Parte HW: Descargue la siguiente plantilla y descomprimala en una ruta sin espacios y corta. Ahora abra el proyecto Quartus y abra Qsys(Seleccione system.qsys). Una vez en Qsys, agregue el modulo llamado "Frame Reader" y configure de la siguiente manera:  El Frame Reader, leerá directamente de la RAM una sección de memoria con las características que están en el...

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Thursday, 23 November 2017

Escrito por Fabio Andres En este proyecto se utilizan las herramientas la De0-nano (FPGA, Procesador NIOS II, Memoria y pines) en conjunto con una pantalla touch para lograr la visualizacion de un fractal Mandelbrot, y lograr ver las ventajas que tiene poner Hardware en paralelo con Software para realizar procesos matemáticos complejos como los utilizados en la realización de fractales. El procesador se programa en lenguaje C y la FPGA en el lenguaje de descripción de Hardware...

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Thursday, 23 November 2017

Written by Jesus Basado en la practica de PicoCtrl del Prof. Yair Linn. OBJETIVOS  Aprender como funciona y como programar el microcontrolador PicoCtrl, adquiriendo conocimiento de como funciona un microcontrolador. INTRODUCCIONUn microcontrolador es un circuito integrado de alta escala de integración que incorpora la mayor parte de los elementos que configuran un controlador. Un microcontrolador dispone normalmente de los siguientes componentes: Procesador o UCP (Unidad...

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