Written by Fabio Andres


  NIOS II PROCESSOR - Hardware

Nios II is an embed processor of structure of 32 bits specifically designed for FPGAs of the brand Altera (Intel).  Nios II has many improvements with the original architecture niosll/e, therefore is more suitable for a huge kinds of informatics applications such as DSP and control systems, moreover, Nios II processor is the world's most versatile processor, according to Gartner Research, and is the most widely used soft processor in the FPGA industry. The Nios II processor delivers unprecedented flexibility for your cost-sensitive, real-time, safety-critical (DO-254), ASIC-optimized, and applications processing needs. The Nios II processor supports all Intel FPGA and SoC families.

PROCESSOR CONFIGURATION

 

In the previous imagen shows the different modules that conform the Nios II, the modules debug option, fixed and optional are configurable.  

 

FEATURES:

 

  1. APPLICATION PROCESSING: With a simple configuration, the core of the fast Nios II processor can use an unit of memory management unit (MMU) for run embedded Linux.  Open code and Linux’s compatible versions are available for Nios II processor.
  2. ECONOMY: With only 600 logic elements, the Nios II processor core is ideal for applications of micro-controllers. The embedded Software Tools, Software, and Middleware it can be free.
  3. REAL TIME: A yield without jitter absolutely deterministic in real time with hardware. These are some functions in real time:
  • Vector controller of interruption
  • Memory of rigid structure
  • Nios II processor is the processor in real time ideal for use with the hardware accelerators based on DPS for provide results in real time with high yield.

 

PROCESS:

 These are the steps for the design of this practice.

1. Firstly we create a new quartus project file (.qpf) with system builder tool for de0nano soc boards, in this case the name of the archive is NIOS II PRACTICE.

 

 

Finally we click in the GENERATE button and we generate a new quartus project file (.qpf).

2. Save the file that system builder created, for opening the archive is necessary to find a nearest route to main disk, that route must not have spaces or strange symbols.

 

3. Open the archive and find a .qpf file. open the file with Quartus II, in the upper part where it says TOOLS find theoption QSYS and open it. 


(Right-Click on the image and open image in new tab to Magnify)

4. When you click in the QSYS option, you will see a window like this:

 In the left part will appear the IP CATALOG,in this part, you can find all the compliments or modules that you can add or use for the design. 

5. Save your design as Nios II. The first module that you have to add will be the Nios II embedded processor, for that, go to IP CATALOG and search NIOS there will appear NIOS II and you have to double clicking.

 6. Then appear a window similar like this,  choose NIOS/E option.

Both options of Nios work, however Nios / f has the fastest processor and can execute more instructions per second, in this case we choose the version Nios II / e (free option) , then, you click FINISH.

 

7. In IP CATALOG you have to write the word CHIP and inside of the options it will appear the ON-CHIP MEMORY option, double-click in this and then, set the memory capacity to 116000, finally click FINISH.

 

 

 8. Now, go and search the word PLL,  select the Altera PLL module and double-click. 

 When the new window is opened, configure the module selected with a beginning clock of 50 Mhz and then other of 150 Mhz how the image shows.

 

 9. For the next module, write JTAG UART and double-click.

When the configure window opens, everything remains the same as the image. Nothing change.  

 

10. For the next module is necessary add three modules of the same name, but with different functions, go for IP CATALOG and search the word PIO, double-clicking to add each module.

 

 Below it shows the different configurations of PIO ports which will be inputs and outputs.

 The first one will be an entry of 4 bits as the image shows

 

The second port will be an 8-bit output.

 And finally one of 32 bits

 11. Now, search the word UART and choose UART SERIAL, double-click and, in the configuration part, do not change anything. 

12. The last module that we added is the INTERVAL TIMER, we choose and double-click, and the same as the previous item, we do not chance anything. 

13. With all the modules ready, is necessary chance the names to differentiate from each other as the image shows.

Change the names as the image shows.

 

14. To observe how the project is going, go for VIEW and click in schematic

When you double-click, Qsys show you the window with all the modules that you have at the moment with the Inputs and Outputs.

 

 

 

15. Open the module called cpu, and configure vector section as the image shows: 

16. Now it is time to interconnect all the modules that you have added to the qsys design as follows:

 

17. This step is necessary to result the position mistakes that genereted the modules, therefore you go to button system in the top left and double click in assign addreses and assign interrupt numbers , finally all the mistakes disappear. 

 

 

18. Finally you have to generate the HLD file that you can generate in the lower part or in upper part as the imagen shows.


 

19.You can show the instantiation template in order to instantiate our nios ii system in the main module.

 

 

20. Click in CLOSE and return to Quartus II, the next image shows an example about instantiation in the main file.

21. Before compile the project, you have to add a qsys file, as the images show.

22. Now, you can compile the project and check if all is correct

 

 

Solution Source: Download.


 

Written by Holguer Andres
 
 
Welcome to FPGA lover!!!
 
Currently, I am moving all my web courses to a single one(www.fpgalover.com) using solely Terasic/Altera Boards. This Web page will have soon all my tutorials including the content of all my courses among I have:
 
 
While this is done, please I invite you to take a look at the new manuals on the web page, and have a tour, Enjoy, and Love FPGAs!
 
PS: Register to get access to exclusive tutorials and manuals.
 
Best Regards.
 
 

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