DE-Nano FPGA Board Configuration



Pin Assignments:




Pin Assignment Table:



CLOCK
Name Location Direction Standard
CLOCK_50 R8 input 3.3-V LVTTL



LED
Name Location Direction Standard
LED[0] A15 output 3.3-V LVTTL
LED[1] A13 output 3.3-V LVTTL
LED[2] B13 output 3.3-V LVTTL
LED[3] A11 output 3.3-V LVTTL
LED[4] D1 output 3.3-V LVTTL
LED[5] F3 output 3.3-V LVTTL
LED[6] B1 output 3.3-V LVTTL
LED[7] L3 output 3.3-V LVTTL



KEY
Name Location Direction Standard
KEY[0] J15 input 3.3-V LVTTL
KEY[1] E1 input 3.3-V LVTTL



SW
Name Location Direction Standard
SW[0] M1 input 3.3-V LVTTL
SW[1] T8 input 3.3-V LVTTL
SW[2] B9 input 3.3-V LVTTL
SW[3] M15 input 3.3-V LVTTL



SDRAM
Name Location Direction Standard
DRAM_BA[0] M7 output 3.3-V LVTTL
DRAM_BA[1] M6 output 3.3-V LVTTL
DRAM_DQM[0] R6 output 3.3-V LVTTL
DRAM_DQM[1] T5 output 3.3-V LVTTL
DRAM_RAS_N L2 output 3.3-V LVTTL
DRAM_CAS_N L1 output 3.3-V LVTTL
DRAM_CKE L7 output 3.3-V LVTTL
DRAM_CLK R4 output 3.3-V LVTTL
DRAM_WE_N C2 output 3.3-V LVTTL
DRAM_CS_N P6 output 3.3-V LVTTL
DRAM_DQ[0] G2 inout 3.3-V LVTTL
DRAM_DQ[1] G1 inout 3.3-V LVTTL
DRAM_DQ[2] L8 inout 3.3-V LVTTL
DRAM_DQ[3] K5 inout 3.3-V LVTTL
DRAM_DQ[4] K2 inout 3.3-V LVTTL
DRAM_DQ[5] J2 inout 3.3-V LVTTL
DRAM_DQ[6] J1 inout 3.3-V LVTTL
DRAM_DQ[7] R7 inout 3.3-V LVTTL
DRAM_DQ[8] T4 inout 3.3-V LVTTL
DRAM_DQ[9] T2 inout 3.3-V LVTTL
DRAM_DQ[10] T3 inout 3.3-V LVTTL
DRAM_DQ[11] R3 inout 3.3-V LVTTL
DRAM_DQ[12] R5 inout 3.3-V LVTTL
DRAM_DQ[13] P3 inout 3.3-V LVTTL
DRAM_DQ[14] N3 inout 3.3-V LVTTL
DRAM_DQ[15] K1 inout 3.3-V LVTTL
DRAM_ADDR[0] P2 output 3.3-V LVTTL
DRAM_ADDR[1] N5 output 3.3-V LVTTL
DRAM_ADDR[2] N6 output 3.3-V LVTTL
DRAM_ADDR[3] M8 output 3.3-V LVTTL
DRAM_ADDR[4] P8 output 3.3-V LVTTL
DRAM_ADDR[5] T7 output 3.3-V LVTTL
DRAM_ADDR[6] N8 output 3.3-V LVTTL
DRAM_ADDR[7] T6 output 3.3-V LVTTL
DRAM_ADDR[8] R1 output 3.3-V LVTTL
DRAM_ADDR[9] P1 output 3.3-V LVTTL
DRAM_ADDR[10] N2 output 3.3-V LVTTL
DRAM_ADDR[11] N1 output 3.3-V LVTTL
DRAM_ADDR[12] L4 output 3.3-V LVTTL



EEPROM
Name Location Direction Standard
I2C_SCLK F2 output 3.3-V LVTTL
I2C_SDAT F1 inout 3.3-V LVTTL



2x13 GPIO Header
Name Location Direction Standard
GPIO_2[0] A14 inout 3.3-V LVTTL
GPIO_2[1] B16 inout 3.3-V LVTTL
GPIO_2[2] C14 inout 3.3-V LVTTL
GPIO_2[3] C16 inout 3.3-V LVTTL
GPIO_2[4] C15 inout 3.3-V LVTTL
GPIO_2[5] D16 inout 3.3-V LVTTL
GPIO_2[6] D15 inout 3.3-V LVTTL
GPIO_2[7] D14 inout 3.3-V LVTTL
GPIO_2[8] F15 inout 3.3-V LVTTL
GPIO_2[9] F16 inout 3.3-V LVTTL
GPIO_2[10] F14 inout 3.3-V LVTTL
GPIO_2[11] G16 inout 3.3-V LVTTL
GPIO_2[12] G15 inout 3.3-V LVTTL
GPIO_2_IN[0] E15 input 3.3-V LVTTL
GPIO_2_IN[1] E16 input 3.3-V LVTTL
GPIO_2_IN[2] M16 input 3.3-V LVTTL



GPIO_0 connect to GPIO Default
Name Location Direction Standard GPIO Pin Index
GPIO_IN[0] A8 input 3.3-V LVTTL 1
GPIO[0] D3 inout 3.3-V LVTTL 2
GPIO_IN[1] B8 input 3.3-V LVTTL 3
GPIO[1] C3 inout 3.3-V LVTTL 4
GPIO[2] A2 inout 3.3-V LVTTL 5
GPIO[3] A3 inout 3.3-V LVTTL 6
GPIO[4] B3 inout 3.3-V LVTTL 7
GPIO[5] B4 inout 3.3-V LVTTL 8
GPIO[6] A4 inout 3.3-V LVTTL 9
GPIO[7] B5 inout 3.3-V LVTTL 10
GPIO[8] A5 inout 3.3-V LVTTL 13
GPIO[9] D5 inout 3.3-V LVTTL 14
GPIO[10] B6 inout 3.3-V LVTTL 15
GPIO[11] A6 inout 3.3-V LVTTL 16
GPIO[12] B7 inout 3.3-V LVTTL 17
GPIO[13] D6 inout 3.3-V LVTTL 18
GPIO[14] A7 inout 3.3-V LVTTL 19
GPIO[15] C6 inout 3.3-V LVTTL 20
GPIO[16] C8 inout 3.3-V LVTTL 21
GPIO[17] E6 inout 3.3-V LVTTL 22
GPIO[18] E7 inout 3.3-V LVTTL 23
GPIO[19] D8 inout 3.3-V LVTTL 24
GPIO[20] E8 inout 3.3-V LVTTL 25
GPIO[21] F8 inout 3.3-V LVTTL 26
GPIO[22] F9 inout 3.3-V LVTTL 27
GPIO[23] E9 inout 3.3-V LVTTL 28
GPIO[24] C9 inout 3.3-V LVTTL 31
GPIO[25] D9 inout 3.3-V LVTTL 32
GPIO[26] E11 inout 3.3-V LVTTL 33
GPIO[27] E10 inout 3.3-V LVTTL 34
GPIO[28] C11 inout 3.3-V LVTTL 35
GPIO[29] B11 inout 3.3-V LVTTL 36
GPIO[30] A12 inout 3.3-V LVTTL 37
GPIO[31] D11 inout 3.3-V LVTTL 38
GPIO[32] D12 inout 3.3-V LVTTL 39
GPIO[33] B12 inout 3.3-V LVTTL 40



GPIO_1 connect to GPIO Default
Name Location Direction Standard GPIO Pin Index
GPIO1_IN[0] T9 input 3.3-V LVTTL 1
GPIO1[0] F13 inout 3.3-V LVTTL 2
GPIO1_IN[1] R9 input 3.3-V LVTTL 3
GPIO1[1] T15 inout 3.3-V LVTTL 4
GPIO1[2] T14 inout 3.3-V LVTTL 5
GPIO1[3] T13 inout 3.3-V LVTTL 6
GPIO1[4] R13 inout 3.3-V LVTTL 7
GPIO1[5] T12 inout 3.3-V LVTTL 8
GPIO1[6] R12 inout 3.3-V LVTTL 9
GPIO1[7] T11 inout 3.3-V LVTTL 10
GPIO1[8] T10 inout 3.3-V LVTTL 13
GPIO1[9] R11 inout 3.3-V LVTTL 14
GPIO1[10] P11 inout 3.3-V LVTTL 15
GPIO1[11] R10 inout 3.3-V LVTTL 16
GPIO1[12] N12 inout 3.3-V LVTTL 17
GPIO1[13] P9 inout 3.3-V LVTTL 18
GPIO1[14] N9 inout 3.3-V LVTTL 19
GPIO1[15] N11 inout 3.3-V LVTTL 20
GPIO1[16] L16 inout 3.3-V LVTTL 21
GPIO1[17] K16 inout 3.3-V LVTTL 22
GPIO1[18] R16 inout 3.3-V LVTTL 23
GPIO1[19] L15 inout 3.3-V LVTTL 24
GPIO1[20] P15 inout 3.3-V LVTTL 25
GPIO1[21] P16 inout 3.3-V LVTTL 26
GPIO1[22] R14 inout 3.3-V LVTTL 27
GPIO1[23] N16 inout 3.3-V LVTTL 28
GPIO1[24] N15 inout 3.3-V LVTTL 31
GPIO1[25] P14 inout 3.3-V LVTTL 32
GPIO1[26] L14 inout 3.3-V LVTTL 33
GPIO1[27] N14 inout 3.3-V LVTTL 34
GPIO1[28] M10 inout 3.3-V LVTTL 35
GPIO1[29] L13 inout 3.3-V LVTTL 36
GPIO1[30] J16 inout 3.3-V LVTTL 37
GPIO1[31] K15 inout 3.3-V LVTTL 38
GPIO1[32] J13 inout 3.3-V LVTTL 39
GPIO1[33] J14 inout 3.3-V LVTTL 40